1/10 product preview october 2005 this is a preliminary information on a new product now in development. details are subjet to change without notice STL100NH3LL n-channel 30v - 0.0032 ? - 25a powerflat? (6x5) stripfet? iii mosfet table 1: general features typical r ds (on) = 0.0032 ? @ 10v improved die-to-footprint ratio very low profile package (1mm max) very low thermal resistance conduction losses reduced switching losses reduced description the STL100NH3LL ut ilizes the latest advanced design rules of st?s proprietary stripfet? tech - nology. this process complete to unique metalliza - tion technique realised the most advanced low voltage mosfet in powerflat(6x5). the chip- scaled powerflat? package allows a significant board space saving, still boosting the perfor - mance. applications high-efficiency dc-dc converters synchronous rectification table 2: order codes figure 1: package figure 2: internal schematic diagram type v dss r ds(on) i d STL100NH3LL 30 v < 0.0035 ? 25 a (1) powerflat (6x5) sales type marking package packaging STL100NH3LL l100nh3ll powerflat?( 6x5 ) tape & reel rev. 4
STL100NH3LL 2/10 table 3: absolute maximum ratings table 4: thermal data table 5: avalanche characteristics electrical characteristics (t case =25c unless otherwise specified) table 6: on/off symbol parameter value unit v ds drain-source voltage (v gs = 0) 30 v v gs gate- source voltage 16 v i d (2) drain current (continuous) at t c = 25c 100 a i d drain current (continuous) at t c = 100c 15.6 a i dm (3) drain current (pulsed) 100 a i d (1) drain current (continuous) at t c = 25c 25 a p tot (2) total dissipation at t c = 25c 80 w p tot (1) total dissipation at t c = 25c 4 w derating factor 0.03 w/c t stg t j storage temperature operating junction temperature range -55 to 150 c rthj- c thermal resistance junction-case ( drain) (steady state) 1.56 c/w rthj-pcb (4) thermal operating junction-pcb 31.3 c/w symbol parameter max value unit i av not-repetitive avalanche current (pulse width limited by t j max) 12.5 a e as single pulse avalanche energy (starting t j = 25 c, i d = i av , v dd = 24 v) 1.3 j symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 a, v gs = 0 30 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating v ds = max rating, t c = 125 c 1 10 a a i gss gate-body leakage current (v ds = 0) v gs = 16v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 1 v r ds(on) static drain-source on resistance v gs = 10v, i d = 12.5 a v gs = 4.5v, i d =12.5 a 0.0032 0.004 0.0035 0.005 ? ?
3/10 STL100NH3LL electrical characteristics (continued) table 7: dynamic table 8: source drain diode note: (1)the value is according r thj-pcb (2)the value is according r thj-c (3) pulse width limited by safe operating area. (4) when mounted on fr-4 board of 1 in 2 , 2oz cu, t < 10 sec (5) pulsed: pulse duration = 300 s, duty cycle 1.5% symbol parameter test conditions min. typ . max. unit g fs (5) forward transconductance v ds = 10 v , i d =12,5 a 30 s c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds = 25v, f = 1 mhz, v gs = 0 4450 655 50 pf pf pf t d(on) t r t d(off) t r turn-on delay time rise time turn-off delay time fall time v dd = 15 v, i d = 12.5 a, r g = 4.7 ? v gs = 10 v (see figure 15) 18 50 75 8 ns ns ns ns q g q gs q gd total gate charge gate-source charge gate-drain charge v dd = 15v, i d = 25 a, v gs = 4.5v (see figure 17) 30 12.5 10 40 nc nc nc r g gate input resistance f=1 mhz gate dc bias = 0 test signal level = 20mv open drain 1 2 3 ? symbol parameter test conditions min. typ . max. unit i sd i sdm (3) source-drain current source-drain current (pulsed) 25 100 a a v sd (4) forward on voltage i sd = 25 a, v gs = 0 1.3 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 25 a, di/dt = 100a/s v dd = 25 v, t j = 150c (see test circuit, figure 16) 32 34 2.1 ns nc a
STL100NH3LL 4/10 figure 3: safe operating area figure 4: output characteristics figure 5: transconductance figure 6: thermal impedance figure 7: transfer characteristics figure 8: static drain-source on resistance
5/10 STL100NH3LL figure 9: gate charge vs gate-source voltage figure 10: normalized gate thereshold volt - age vs temperature figure 11: normalized on resistance vs tem - perature figure 12: capacitance variations figure 13: normalized bvdss vs temperature figure 14: source-drain diode forward char - acteristics
STL100NH3LL 6/10 figure 15: switching times test circuit for resistive load figure 16: test circuit for inductive load switching and diode recovery times figure 17: gate charge test circuit
7/10 STL100NH3LL in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com
STL100NH3LL 8/10 dim. mm. inch min. typ max. min. typ. max. a 0.80 0.83 0.93 0.031 0.032 0.036 a1 0.02 0.05 0.0007 0.0019 a3 0.20 0.007 b 0.35 0.40 0.47 0.013 0.015 0.018 d 5.00 0.196 d1 4.75 0.187 d2 4.15 4.20 4.25 0.163 0.165 0.167 e 6.00 0.236 e1 5.75 0.226 e2 3.43 3.48 3.53 0.135 0.137 0.139 e4 2.58 2.63 2.68 0.103 0.105 e 1.27 0.050 l 0.70 0.80 0.90 0.027 0.031 0.035 powerflat? (6x5) mechanical data
9/10 STL100NH3LL table 9: revision history date revision description of changes 18-apr-2005 1 first release 20-jun-2005 2 updated mechanical data 22-jun-2005 3 new r g value on table 6 10-oct-2005 4 inserted ecopack indication
STL100NH3LL 10/10 i nformation furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the con sequence s o f use of such information nor for any infringement of patents or other rights of third parties which may result from its use. n o license is grante d b y implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicatio n are subjec t t o change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics produ cts are no t a uthorized for use as critical components in life support devices or systems without express written approval of stmicroelectron ics. the st logo is a registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com
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